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IBIS

Conference Schedule: Click here to open.

Instructions for presenters (oral and poster): Click here to open.

FINAL PROGRAM

WEDNESDAY, 11 MAY 2016

08:30 Registration opens

08:30 Exhibition opens

08:50 - 10:30 Session 9: Novel Techniques for Signal and Power Integrity

Chair: J. Schutt-Aine', A. Maffucci

08:50 - 09:10

Investigation of the power-clock network impact on adiabatic logic

N. Jeanniot (1), A. Todri-Sanial (1), P. Nouet (1), G. Pillonnet (2), H. Fanet (2)

(1) University of Montpellier, France; (2) CEA-LETI-MINATEC, France

09:10 - 09:30

Navigating PCB stackup layer assignments for optimized SI and PI performance in high speed, high power designs (slides)

C.M. Smutzer, M.J. Degerstrom, B.K. Gilbert

Mayo Clinic, USA

09:30 - 09:50

Ripple analysis: identify and quantify reflective interference through ISI decomposition (student paper) (slides)

R.J. Allred (1,2), B. Katz (2), C. Furse (1)

(1) University of Utah, USA; (2) SiSoft, USA

09:50 - 10:10

Pessimism removal in a system analysis of a 28Gbps SERDES link (slides)

O. Bayet (1), M. Cereda (2)

(1) STMicroelectronics, France; (2) STMicroelectronics, Italy

10:10 - 10:30

SIPI co-extraction and SPICE co-simulation for package on-die decap optimization

A. Ciccomancini Scogna (1), L.K. Teoh (2)

(1) CST, Germany; (2) eASIC, Malaysia

10:30 - 11:00 Coffee break

11:00 - 12:20 Session 10: TSV and 3DIC

Chair: G. Signorini, A. Chandrasekhar

11:00 - 11:20

TSVs embedded in a microfluidic heat sink: high-frequency characterization and thermal modeling (student paper) (slides)

H. Oh, Y. Zhang, T.E. Sarvey, G.S. May, M.S. Bakir

Georgia Institute of Technology, USA

11:20 - 11:40

On the upper bound of total uncorrelated crosstalk in large through silicon via arrays (student paper) (slides)

D. Dahl (1), T. Reuschel (1), X. Duan (2), I. Ndip (3), K.-D. Lang (3), C. Schuster (1)

(1) Technische Universität Hamburg-Harburg, Germany; (2) IBM, Germany; (3) Fraunhofer Institute for Reliability and Microintegration (IZM), Germany

11:40 - 12:00

Impact of voltage bias on through silicon vias (TSV) depletion and crosstalk (slides)

S. Piersanti (1), F. de Paulis (1), A. Orlandi (1), J. Fan (2), J. Drewniak (2), B. Achkir (3)

(1) University of L'Aquila, Italy; (2) Missouri University of Science and Technology, USA; (3) Cisco System Inc., USA

12:00 - 12:20

High frequency modeling of through silicon capacitors (TSC) architectures in silicon interposer (student paper) (slides)

K. Dieng (1), C. Bermond (1), P. Artillan (1), O. Guiller (2), T. Lacrevaz (1), S. Joblot (2), G. Houzet (1), A. Farcy (2), Y. Lamy (3), B. Fléchet (1)

(1) Université de Savoie Mont-Blanc, France; (2) STMicroelectronics, France; (3) Université Grenoble Alpes, France

12:20 - 12:40 Closing ceremony

12:40 Exhibition closes

13:45 - 18:00 19th European IBIS Summit

Organized by: IBIS Open Forum

13:45 Sign In, Refreshments

14:00 - 14:10

Welcome and Introductions

Lance Wang

IO Methodology, Vice-chair IBIS Open Forum, USA

14:10 - 14:20

IBIS Update

Mike LaBonte (1), Lance Wang (2)

(1) SiSoft, USA; (2) IO Methodology, USA

14:20 - 14:50

Understanding IBIS-AMI Simulations

Richard Allred

SiSoft, University of Utah, USA

14:50 - 15:20

Using IBIS-AMI Models to Maximize Data Rate Given SerDes EQ and Channel ISI/Loss

Donald Telian

SiGuys, USA

15:20 - 15:40

Overclocking Issues

Michael Schaeder

Zuken, Germany

15:40 - 16:10

IBIS + Mpilog: Current and Future Developments on I/O-Buffer Modeling

Gianni Signorini (1), Claudio Siviero (2), Igor Simone Stievano (2), Stefano Grivet-Talocia (2), Michael Mirmak (3)

(1) Intel Corp., Germany; (2) Politecnico di Torino, Italy; (3) Intel Corp., USA

16:10 - 16:25 Coffee Break

16:25 - 16:55

Surrogate Models for IC Buffers: A Top-down Approach

Cherif Diouf (1), Mahai Telescu (2), N. Tanguy (2), Igor Simone Stievano (3), Flavio G. Canavero (3)

(1) École Nationale d'Ingénieurs de Brest, France; (2) Université de Bretagne Occidentale, France; (3) Politecnico di Torino, Italy

16:55 - 17:35

Multiport I/O Model Computation for Power-Aware SI Simulation

Wael Dghais (1), Fathi Bellamine (2)

(1) Université de Sousse, Tunisia; (2) Université de Carthage, Tunisia

17:35 - 17:55

On-Die Decoupling Model Improvements for IBIS Power Aware Models

Randy Wolff

Micron Technology, USA

17:55 - 18:00

Closing Remarks

Lance Wang

IO Methodology, Vice-chair IBIS Open Forum, USA

18:00 Meeting Ends