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Conference Schedule: Click here to open.

Instructions for presenters (oral and poster): Click here to open.

FINAL PROGRAM

TUESDAY, 10 MAY 2016

08:00 Registration opens

08:30 Exhibition opens

08:30 - 09:30 Session 5: Noise Analysis and Reduction Techniques

Chair: D. Gope, R. Araneo

08:30 - 08:50

Simulation-based analysis on EMI effect in LPDDR interface for mitigating RFI in a mobile environemnt

S. Kim, S. Moon, S. Lee, D. Yi, G. Park, S. Shin, S. Pae

Samsung Electronics, South Korea

08:50 - 09:10

Novel absorptive design of common-mode filter at desired frequency band (student paper)

P.-J. Li, C.-H. Cheng, Y.-C. Tseng, T.-L. Wu

National Taiwan University, Taiwan

09:10 - 09:30

Higher-order virtual ground fence design for filtering power plane noise

A.E. Engin (1), I. Ndip (2), K.-D. Lang (2)

(1) San Diego State University, USA; (2) Fraunhofer-Institut fuer Zuverlaessigkeit und Mikrointegration (IZM), Germany

09:30 - 10:30 Session 6: Power Distribution Networks

Chair: A. E. Engin, G. Antonini

09:30 - 09:50

Effect of via-transitions on signal integrity using power transmission lines (student paper)

D.C. Zhang, M. Swaminathan, D. Keezer

Georgia Institute of Technology, USA

09:50 - 10:10

Power delivery impedance impact of power gating schemes

S. Shekhar (1), A.K. Jain (1), N. Winer (2)

(1) Intel Corporation, USA; (2) Intel Corporation, Israel

10:10 - 10:30

A clustering technique for fast electrothermal analysis of on-chip power distribution networks (slides)

A. Magnani (1), M. de Magistris (1), A. Maffucci (2), A. Todri-Sanial (3)

(1) University Federico II, Italy; (2) University of Cassino and Southern Lazio, Italy; (3) University of Montpellier, France

10:30 - 11:00 Coffee break

11:00 - 12:20 Session 7: Special Session on Model Order Reduction

Chair: W. Schilders, P. Triverio

11:00 - 11:20

Stability preserving post-processing methods applied in the Loewner framework (slides)

I.V. Gosea (1), A.C. Antoulas (2)

(1) Jacobs University Bremen, Germany; (2) Rice University, USA

11:20 - 11:40

Efficient time-domain variability analysis using parameterized model-order reduction

Y. Tao, B. Nouri, M. Nakhla, R. Achar

Carleton University, Canada

11:40 - 12:00

Transfer function modeling for the buck converter (slides)

S. Lefteriu, C. Labarre

Ecole des Mines de Douai, France

12:00 - 12:20

Accelerating time domain simulations of PLLs (student paper) (slides)

G. De Luca (1), W.H.A. Schilders (1), P. Bolcato (2), R. Larcheveque (2), J. Rommes (2)

(1) TU Eindhoven, The Netherlands; (2) Mentor Graphics, France

12:20 - 14:00 Lunch break

14:00 - 15:00 Session 8: Electromagnetic Modeling

Chair: F. Canavero, W. Bandurski

14:00 - 14:20

IR drop analysis of high-speed PCBs using 3D planar EM technology (slides)

J. Sercu

Keysight Technologies, Belgium

14:20 - 14:40

Extension of 2.5D PEEC for coplanar structures in power distribution network analysis

B.P. Nayak, S.R. Vedicherla, D. Gope

Indian Institute of Science, India

14:40 - 15:00

Digital wave formulation of quasi-static partial element equivalent circuit method (slides)

P. Belforte (1), L. Lombardi (2), D. Romano (2), G. Antonini(2)

(1) Independent Researcher; (2) UniversitÓ degli Studi dell'Aquila, Italy

15:00 - 15:45 Industry Forum (part 1)

Chair: S. Grivet-Talocia, C. Schuster

15:00 - 15:15

Fully automated EDA for datacenter platform level SI/PI analysis (slides)

Dave Figueroa

Intel, USA

15:15 - 15:30

Relevant challenges from industry for future systems (slides)

Hubert Harrer

IBM, Germany

15:30 - 15:45

High speed data event horizon sparks signal integrity conundrums (slides)

Richard Mellitz

Intel, USA

15:45 - 16:15 Coffee break

16:15 - 17:30 Industry Forum (part 2)

Chair: S. Grivet-Talocia, C. Schuster

16:15 - 16:30

7 challenging SI/PI problems that have no existing solution (slides)

Donald Telian

SIGuys, USA

16:30 - 16:45

Analog verification of crosstalk effects in multi-radio RF transceiver design: status, challenges and proposed solutions (slides)

Pietro Brenner

Intel, Germany

16:45 - 17:00

Electrical specifications to physical layout: bridging the performance, schedule and cost gaps (slides)

Arun Chandrasekhar

Intel, India

17:00 - 17:30 Open discussion

18:00 Exhibition closes

18:30 Gala dinner